Frequency dividers are commonly used to reduce a frequency of a clock signal in a circuit by an integer (e.g., 2, 3, 4, and so forth). For example, in some electronic systems, a frequency divider may down-convert a signal from a first frequency to a second, lower frequency.
A frequency divider may be part of a phase-locked loop (PLL), which may generate an output signal having a desired frequency. A PLL may include a voltage controlled oscillator (VCO) that may generate a local oscillator (LO) signal having a frequency dependent on a control voltage, which may be generated by a phase detector/charge pump/loop filter (PFD/CP/LPF). The PFD/CP/LPF may generate the control voltage by comparing a reference signal to the LO signal (e.g., via feedback). Thus, the LO signal may be prevented from drifting to a different frequency value.
The reference signal may have a lower frequency than the LO signal, and thus, the PLL may use a frequency divider such that the frequency of the LO signal is a multiple of the frequency of the reference signal. In some applications, a processor may control the frequency divider such that the frequency divider may divide the LO signal by various divisor values. Thus, the PLL may generate the LO signal for transmitting and/or receiving at a plurality of frequencies.